The present invention relates to semiconductor devices in which a ferroelectric material or a high dielectric material is used for a capacitive insulating film, and methods for fabricating the devices.
Semiconductor devices in which a ferroelectric material or a high dielectric material is used for a capacitive insulating film have residual polarization that exhibits hysteresis characteristics, and a high dielectric constant. Such semiconductor devices therefore may replace semiconductor devices that have a capacitive insulating film made of silicon oxide or silicon nitride, in the field of nonvolatile memory devices and DRAM devices.
However, ferroelectric materials and high dielectric materials, which are oxides whose crystal structure determines the physical characteristics thereof, are affected greatly by hydrogen reduction. Nevertheless, MOS-transistor formation process, multilevel-interconnect formation process, and passivation-film formation process, for example, include many process steps in which not only hydrogen gas but also, for example, silane gas, resist material, and water (moisture) that contain hydrogen atoms are used.
In view of this, technology has recently been proposed in which a hydrogen-barrier layer is provided to the lateral portion of the capacitors, covering each capacitor element itself, or with pluralities of the capacitors as units, the entireties.
(First prior art example)
Hereinafter, a semiconductor device that has a capacitive insulating film using a ferroelectric material in accordance with a first prior art example will be described with reference to FIG. 32 (see Japanese Laid-Open Publication No. 2001-237393, for example.)
As shown in FIG. 32, a MOS switching transistor 2 is formed on a semiconductor substrate 1. The MOS switching transistor 2 is covered by an isolation layer 4 made of an oxide of silicon, such as SiO2 (TEOS) or BPSG (borophosphorosilicate glass). A capacitor is formed on the isolation layer 4 so as to be located over the drain region of the MOS switching transistor 2, and the capacitor is composed of a lower electrode 7 made of, e.g., platinum, a dielectric layer 8 made of a ferroelectric or paraelectric material, and an upper electrode 9 made of, e.g., platinum.
The drain region of the MOS switching transistor 2 is electrically connected to the lower electrode 7 of the capacitor via an oxygen-barrier layer 6 formed underneath the lower electrode 7, and via a contact formed by filling a contact hole 3 formed in the isolation layer 4 with doped polysilicon.
In this prior art example, a first hydrogen-barrier layer 5 made of silicon nitride is buried in a peripheral portion of the isolation layer 4 located under the capacitor. Further, the capacitor-including region of the isolation layer 4 is patterned in its peripheral portion so as to have a mesa shape, so that the end portion of the first hydrogen-barrier layer 5 is exposed. A second hydrogen-barrier layer 10 covers the mesa-shaped portion, that is, the upper surface and lateral/edge faces of the upper electrode 9 of the capacitor, the lateral/edge faces of the dielectric layer 8, and the lateral/edge faces of the portion of the isolation layer 4 located on the first hydrogen-barrier layer 5. Further, the exposed portion of the first hydrogen-barrier layer 5 is connected to the end portion, L-shaped in cross section, of the second hydrogen-barrier layer 10.
In this manner, the capacitor of the first prior art example is covered by the first hydrogen-barrier layer from underneath and by the second hydrogen-barrier layer 10 from above and laterally.
(Second prior art example)
Next, a semiconductor device that has a capacitive insulating film using a ferroelectric or high dielectric material in accordance with a second prior art example will be described with reference to FIG. 33 (see Japanese Laid-Open Publication No. 11-126881, for example.)
As shown in FIG. 33, a plurality of memory cell transistors 102 are formed as semiconductor active devices on a silicon substrate 101. In this example, the memory cell transistors 102 are the semiconductor active devices that are formed below a plurality of information-storing capacitors each composed of a lower electrode 108, a high ferroelectric material 109, and an upper electrode 110.
Between the capacitor layer and the transistor layer, an interlayer dielectric layer 104 for electrically isolating the layers from each other is formed. The capacitor layer is electrically connected to the transistor layer via first and second plugs 105 and 106.
Provided between the interlayer dielectric layer 104 and the capacitor layer is a hydrogen-diffusion-prevention layer 107 made of an insulator in which hydrogen diffuses at a lesser extent than in the interlayer dielectric layer 104.
A hydrogen-absorption-dissociation-prevention layer 111 covers the top and lateral faces of the upper electrode 110 of the capacitor layer in such a manner that the end portion of the hydrogen-absorption-dissociation-prevention layer 111 is connected with the lateral/edge faces of the hydrogen-diffusion-prevention layer 107.
An interlayer dielectric film 112 is formed on the interlayer dielectric layer 104 as well as on the hydrogen-absorption-dissociation-prevention layer 111. On the interlayer dielectric film 112, an upper interconnect layer 114 is formed. The upper interconnect layer is electrically connected to a peripheral transistor 103 formed on the silicon substrate 101 via a connection plug 113 formed in the interlayer dielectric film 112, and via the first and second plugs 105 and 106 formed in the interlayer dielectric layer 104.
In this manner, the information-storing capacitors in accordance with the second prior art example are covered by the hydrogen-diffusion-prevention layer 107 from underneath and by the hydrogen-absorption-dissociation-prevention layer 111 from above and laterally.
However, as in the first and second prior art examples, in a structure in which a hydrogen-barrier layer is provided to the lateral portion of the capacitors as well, to cover each capacitor element itself, or with pluralities of the capacitors as units, the entireties, the upper hydrogen-barrier film is in contact with a lower hydrogen-barrier film in a small area, which results in the problem that the barrier against hydrogen is insufficient.
Specifically, the first prior art example employs the structure in which the upper hydrogen-barrier layer 10 that is L-shaped in cross section is directly connected to the end portion of the lower hydrogen-barrier film 5. In this structure, the upper hydrogen-barrier film 10, in particular, has a single-layer structure against hydrogen entering from the lateral portion of the capacitor, such that it is difficult for the hydrogen-barrier film 10 to have a sufficient coating-film thickness in the bending portions that are L-shaped in cross section.
Also, the second prior art example employs the structure in which the upper hydrogen-barrier film 111 is connected to the lower hydrogen-barrier film 107 along the end face thereof alone, causing the connection area to be very small.
Accordingly, in either of these structures, the barrier against hydrogen is insufficient in the connection portion where the upper and lower hydrogen-barrier films are connected with each other.
Moreover, as in the second prior art example, in a case of a structure in which a hydrogen-barrier film covers a plurality of capacitors as a whole, it is normally difficult to connect bit lines, which are provided above the memory cell regions (more specifically, above the capacitors), to selective transistors, which are located below the capacitors, in such a manner that the memory cell regions do not increase in area, while at the same time the hydrogen-barrier film, located under the bit lines and covering the capacitors, is avoided, for the purpose of increasing the layout flexibility.